1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) and, specifically, to a semiconductor IC having a plurality of standard cells.
2. Description of Related Art
As a layout design technology for forming an IC on a semiconductor substrate in a short time, a standard cell methodology is widely used. Specifically, small scale circuits such as an inverter circuit, a NAND circuit and the like are registered as standard cells in a cell library, and the semiconductor IC is designed by arranging standard cells in a row.
By the way, both gate pitch and gate length of MOSFETs (metal oxide semiconductor field effect transistor) have been decreasing with miniaturization of semiconductor ICs in recent years. Therefore, the variation of MOSFET performance is caused by the variation in the gate length since it is difficult to control gate length in the photolithography process. To solve this problem, a semiconductor IC is disclosed in Japanese Unexamined Patent Publication No. 9-289251 which has gate electrodes with the same gate length formed at the same pitch by inserting a dummy MOSFET between two standard cells. Thus, the variation in the gate length in photolithography process is reduced.
Further, to reduce the number of standard cells registered in a cell library, standard cell arrays having different drive capability are produced by overlapping diffusion layers of a plurality of registered standard cells in Japanese Unexamined Patent Publication No. 2005-229061.
However, the invention in Japanese Unexamined Patent Publication No. 9-289251 reverses the miniaturization of semiconductor ICs since it requires inserting dummy MOSFETs between each standard cell.
Victor Chan et al. reported that the variation in MOSFET ON current to LOD (Length of Diffusion) becomes pronounced as the miniaturization of semiconductor ICs advances in their paper “Strain for CMOS performance Improvement” at IEEE 2005 Custom Integrated Circuits Conference. Specifically, the smaller the LOD is, the wider the variation in ON current is. To the contrary, if LOD is larger than certain value, ON current becomes constant. Therefore, even if a MOSFET has the same designed ON current, ON current can be different according to the size of LOD in practice. This problem cannot be solved in Japanese Unexamined Patent Publications No. 9-289251 and No. 2005-229061.